1. Clock divider – divide the Altera system 50 MHz clock down to produce a 1 Hz clock to drive the seconds counto Use D flip flops and logic gates to create a Divide by 5 circuit Divide by 10 circuit Connect the divide by 5 and 10 counters together to produce the 1 Hz clock signal Block schematic implementation required. No credit will be awarded for circuits created with Verilog modules.