*5.15 This problem illustrates the central point in the electronics revolution that has been in effect for the past four decades: By continually reducing the MOSFET size, we are able to pack more devices on an IC chip. Gordon Moore, co-founder of Intel Corporation, predicted this exponential growth of chip-packing density very early in the history of the development of the integrated circuit in the formulation that has become known as Moore’s law. The table on the next page shows four technology generations, each characterized by the minimum possible MOSFET channel length (row 1). In going from one generation to another, both L and tox are scaled by the same factor. The power supply utilized VDD is also scaled by the same factor, to keep the magnitudes of all electrical fields within the device unchanged. Unfortunately, but for good reasons, Vt cannot be scaled similarly. Complete the table entries, noting that row 5 asks for the transconductance parameter of an NMOS transistor with W/L = 10; row 9 asks for the value of ID obtained with V GS = VDS = VDD; row 10 asks for the power P = VDDID dissipated in the circuit. An important quantity is the power density, P/A, asked for in row 11. Finally, you are asked to find the number of transistors that can be placed on an IC chip fabricated in each of the technologies in terms of the number obtained with the 0.5-μm technology (n).

15 1 - *5.15 This problem illustrates the central point in the electronics revolution that has been in effect for the past four decades: By continually reducing the MOSFET size, we are able to pack more devices on an IC chip. Gordon Moore, co-founder of Intel Corporation, predicted this exponential growth of chip-packing density very early in the history of the development of the integrated circuit in the formulation that has become known as Moore’s law. The table on the next page shows four technology generations, each characterized by the minimum possible MOSFET channel length (row 1). In going from one generation to another, both L and tox are scaled by the same factor. The power supply utilized VDD is also scaled by the same factor, to keep the magnitudes of all electrical fields within the device unchanged. Unfortunately, but for good reasons, Vt cannot be scaled similarly. Complete the table entries, noting that row 5 asks for the transconductance parameter of an NMOS transistor with W/L = 10; row 9 asks for the value of ID obtained with V GS = VDS = VDD; row 10 asks for the power P = VDDID dissipated in the circuit. An important quantity is the power density, P/A, asked for in row 11. Finally, you are asked to find the number of transistors that can be placed on an IC chip fabricated in each of the technologies in terms of the number obtained with the 0.5-μm technology (n).

This content is for Premium members only.
sign up for premium and access unlimited solutions for a month at just 5$(not renewed automatically)


images - *5.15 This problem illustrates the central point in the electronics revolution that has been in effect for the past four decades: By continually reducing the MOSFET size, we are able to pack more devices on an IC chip. Gordon Moore, co-founder of Intel Corporation, predicted this exponential growth of chip-packing density very early in the history of the development of the integrated circuit in the formulation that has become known as Moore’s law. The table on the next page shows four technology generations, each characterized by the minimum possible MOSFET channel length (row 1). In going from one generation to another, both L and tox are scaled by the same factor. The power supply utilized VDD is also scaled by the same factor, to keep the magnitudes of all electrical fields within the device unchanged. Unfortunately, but for good reasons, Vt cannot be scaled similarly. Complete the table entries, noting that row 5 asks for the transconductance parameter of an NMOS transistor with W/L = 10; row 9 asks for the value of ID obtained with V GS = VDS = VDD; row 10 asks for the power P = VDDID dissipated in the circuit. An important quantity is the power density, P/A, asked for in row 11. Finally, you are asked to find the number of transistors that can be placed on an IC chip fabricated in each of the technologies in terms of the number obtained with the 0.5-μm technology (n).

already a member please login


5   +   3   =