5.23 An NMOS transistor, fabricated with W = 20 μm and L = 1 μm in a technology for which kn = 100 μA/V2 and Vt = 0.8 V, is to be operated at very low values of vDS as a linear resistor. For v GS varying from 1.0 V to 4.8 V, what range of resistor values can be obtained? What is the available range if (a) the device width is halved? (b) the device length is halved? (c) both the width and length are halved?

23 1 - 5.23 An NMOS transistor, fabricated with W = 20 μm and L = 1 μm in a technology for which kn = 100 μA/V2 and Vt = 0.8 V, is to be operated at very low values of vDS as a linear resistor. For v GS varying from 1.0 V to 4.8 V, what range of resistor values can be obtained? What is the available range if (a) the device width is halved? (b) the device length is halved? (c) both the width and length are halved?

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images - 5.23 An NMOS transistor, fabricated with W = 20 μm and L = 1 μm in a technology for which kn = 100 μA/V2 and Vt = 0.8 V, is to be operated at very low values of vDS as a linear resistor. For v GS varying from 1.0 V to 4.8 V, what range of resistor values can be obtained? What is the available range if (a) the device width is halved? (b) the device length is halved? (c) both the width and length are halved?

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