7.103 Figure P7.103 shows a variation of the feedback-bias circuit of Fig. 7.50. Using a 5-V supply with an NMOS transistor for which V t = 0.8 V, kn = 8 mA/V2, and λ = 0, provide a design that biases the transistor at ID = 1 mA, with V DS large enough to allow saturation operation for a 2-V negative signal swing at the drain. Use 22 M as the largest resistor in the feedback-bias network. What values of R D, R G1, and RG2 have you chosen? Specify all resistors to two significant digits.