7.128 The CE amplifier circuit of Fig. P7.128 is biased with a constant-current source I. It is required to design the circuit (i.e., find values for I, RB, and RC) to meet the following specifications: (a) Rin  10 k. (b) The dc voltage drop across RB is approximately 0.2 V. (c) The open-circuit voltage gain from base to collector is the maximum possible, consistent with the requirement that the collector voltage never fall by more than approximately 0.4 V below the base voltage with the signal between base and emitter being as high as 5 mV. Assume that v sig is a sinusoidal source, the available supply V CC = 5 V, and the transistor has β =100. Use standard 5% resistance values, and specify the value of I to one significant digit. What base-to-collector open-circuit voltage gain does your design provide? If Rsig = RL = 20 k, what is the overall voltage gain?

128 - 7.128 The CE amplifier circuit of Fig. P7.128 is biased with a constant-current source I. It is required to design the circuit (i.e., find values for I, RB, and RC) to meet the following specifications: (a) Rin  10 k. (b) The dc voltage drop across RB is approximately 0.2 V. (c) The open-circuit voltage gain from base to collector is the maximum possible, consistent with the requirement that the collector voltage never fall by more than approximately 0.4 V below the base voltage with the signal between base and emitter being as high as 5 mV. Assume that v sig is a sinusoidal source, the available supply V CC = 5 V, and the transistor has β =100. Use standard 5% resistance values, and specify the value of I to one significant digit. What base-to-collector open-circuit voltage gain does your design provide? If Rsig = RL = 20 k, what is the overall voltage gain?

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images - 7.128 The CE amplifier circuit of Fig. P7.128 is biased with a constant-current source I. It is required to design the circuit (i.e., find values for I, RB, and RC) to meet the following specifications: (a) Rin  10 k. (b) The dc voltage drop across RB is approximately 0.2 V. (c) The open-circuit voltage gain from base to collector is the maximum possible, consistent with the requirement that the collector voltage never fall by more than approximately 0.4 V below the base voltage with the signal between base and emitter being as high as 5 mV. Assume that v sig is a sinusoidal source, the available supply V CC = 5 V, and the transistor has β =100. Use standard 5% resistance values, and specify the value of I to one significant digit. What base-to-collector open-circuit voltage gain does your design provide? If Rsig = RL = 20 k, what is the overall voltage gain?

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