7.7 The expression for the incremental voltage gain Av given in Eq. (7.16) can be written in as A v = − 2VDD −VDS V OV where V DS is the bias voltage at the drain. This expression indicates that for given values of VDD and VOV, the gain magnitude can be increased by biasing the transistor at a lower V DS. This, however, reduces the allowable output signal swing in the negative direction. Assuming linear operation around the bias point, show that the largest possible negative output signal peak vˆo that is achievable while the transistor remains saturated is vˆ o = VDS −VOV 1+ A1v For V DD = 5 V and VOV = 0.5 V, provide a table of values for A v, vˆo, and the corresponding vˆi for VDS = 1 V, 1.5 V, 2 V, and 2.5 V. If k n(W/L) = 1 mA/V2, find ID and RD for the design for which V DS = 1 V.

7 16 - 7.7 The expression for the incremental voltage gain Av given in Eq. (7.16) can be written in as A v = − 2VDD −VDS V OV where V DS is the bias voltage at the drain. This expression indicates that for given values of VDD and VOV, the gain magnitude can be increased by biasing the transistor at a lower V DS. This, however, reduces the allowable output signal swing in the negative direction. Assuming linear operation around the bias point, show that the largest possible negative output signal peak vˆo that is achievable while the transistor remains saturated is vˆ o = VDS −VOV1+  A1v  For V DD = 5 V and VOV = 0.5 V, provide a table of values for A v, vˆo, and the corresponding vˆi for VDS = 1 V, 1.5 V, 2 V, and 2.5 V. If k n(W/L) = 1 mA/V2, find ID and RD for the design for which V DS = 1 V.

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images - 7.7 The expression for the incremental voltage gain Av given in Eq. (7.16) can be written in as A v = − 2VDD −VDS V OV where V DS is the bias voltage at the drain. This expression indicates that for given values of VDD and VOV, the gain magnitude can be increased by biasing the transistor at a lower V DS. This, however, reduces the allowable output signal swing in the negative direction. Assuming linear operation around the bias point, show that the largest possible negative output signal peak vˆo that is achievable while the transistor remains saturated is vˆ o = VDS −VOV1+  A1v  For V DD = 5 V and VOV = 0.5 V, provide a table of values for A v, vˆo, and the corresponding vˆi for VDS = 1 V, 1.5 V, 2 V, and 2.5 V. If k n(W/L) = 1 mA/V2, find ID and RD for the design for which V DS = 1 V.

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