7.93 Using the circuit topology displayed in Fig. 7.48(e), arrange to bias the NMOS transistor at ID = 0.5 mA with VD midway between cutoff and the beginning of triode operation. The available supplies are ±5 V. For the NMOS transistor, Vt = 1.0 V, λ = 0, and kn = 1 mA/V2. Use a gate-bias resistor of 10 M. Specify RS and RD to two significant digits.

93 8 - 7.93 Using the circuit topology displayed in Fig. 7.48(e), arrange to bias the NMOS transistor at ID = 0.5 mA with VD midway between cutoff and the beginning of triode operation. The available supplies are ±5 V. For the NMOS transistor, Vt = 1.0 V, λ = 0, and kn = 1 mA/V2. Use a gate-bias resistor of 10 M. Specify RS and RD to two significant digits.

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images - 7.93 Using the circuit topology displayed in Fig. 7.48(e), arrange to bias the NMOS transistor at ID = 0.5 mA with VD midway between cutoff and the beginning of triode operation. The available supplies are ±5 V. For the NMOS transistor, Vt = 1.0 V, λ = 0, and kn = 1 mA/V2. Use a gate-bias resistor of 10 M. Specify RS and RD to two significant digits.

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