7.97 Design the circuit of Fig. 7.48(e) for a MOSFET having Vt = 1 V and kn = 4 mA/V2. Let VDD = VSS = 5 V. Design for a dc bias current of 0.5 mA and for the largest possible voltage gain (and thus the largest possible RD) consistent with allowing a 2-V peak-to-peak voltage swing at the drain. Assume that the signal voltage on the source terminal of the FET is zero

97 7 - 7.97 Design the circuit of Fig. 7.48(e) for a MOSFET having Vt = 1 V and kn = 4 mA/V2. Let VDD = VSS = 5 V. Design for a dc bias current of 0.5 mA and for the largest possible voltage gain (and thus the largest possible RD) consistent with allowing a 2-V peak-to-peak voltage swing at the drain. Assume that the signal voltage on the source terminal of the FET is zero

This content is for Premium members only.
sign up for premium and access unlimited solutions for a month at just 5$(not renewed automatically)


images - 7.97 Design the circuit of Fig. 7.48(e) for a MOSFET having Vt = 1 V and kn = 4 mA/V2. Let VDD = VSS = 5 V. Design for a dc bias current of 0.5 mA and for the largest possible voltage gain (and thus the largest possible RD) consistent with allowing a 2-V peak-to-peak voltage swing at the drain. Assume that the signal voltage on the source terminal of the FET is zero

already a member please login


7   +   1   =