9.113 Consider the circuit in Fig. 9.40 with the device geometries (in μm) shown in Table P9.113. Let I REF = 225 μA,  Vt  = 0.75 V for all devices, μnCox = 180 μA/V2, μpCox = 60 μA/V2,  VA  = 9 V for all devices, VDD = VSS = 1.5 V. Determine the width of Q6, W, that will ensure that the op amp will not have a systematic offset voltage. Then, for all devices evaluate ID,  VOV ,  VGS , gm, and ro. Provide your results in a table similar to Table 9.1. Also find A 1, A2, the open-loop voltage gain, the input common-mode range, and the output voltage range. Neglect the effect of V A on the bias currents.

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images - 9.113 Consider the circuit in Fig. 9.40 with the device geometries (in μm) shown in Table P9.113. Let I REF = 225 μA,  Vt  = 0.75 V for all devices, μnCox = 180 μA/V2, μpCox = 60 μA/V2,  VA  = 9 V for all devices, VDD = VSS = 1.5 V. Determine the width of Q6, W, that will ensure that the op amp will not have a systematic offset voltage. Then, for all devices evaluate ID,  VOV ,  VGS , gm, and ro. Provide your results in a table similar to Table 9.1. Also find A 1, A2, the open-loop voltage gain, the input common-mode range, and the output voltage range. Neglect the effect of V A on the bias currents.

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