9.118 The two-stage op amp in Figure P9.114 is fabricated in a 65-nm technology having kn = 5.4 × kp = 540 μA/V2 and V tn = −Vtp = 0.35 V. The amplifier is operated with V DD = +1.2 V and VSS = 0 V.(a) With A and B at a dc voltage of VDD/2, perform a dc design that will result in each of Q1, Q2, Q3, and Q4 conducting a drain current of 200 μA and each of Q6 and Q7 conducting a current of 400 μA. Design so that all transistors operate at 0.15-V overdrive voltages. Specify the W/L ratio required for each MOSFET. Present all results in a table. (b) Find the input common-mode range. (c) Find the allowable range of the output voltage. (d) With vA = vid/2 and vB = −vid/2, find the voltage gain vo /vid. Assume an Early voltage of 1.8 V.

118 - 9.118 The two-stage op amp in Figure P9.114 is fabricated in a 65-nm technology having kn = 5.4 × kp = 540 μA/V2 and V tn = −Vtp = 0.35 V. The amplifier is operated with V DD = +1.2 V and VSS = 0 V.(a) With A and B at a dc voltage of VDD/2, perform a dc design that will result in each of Q1, Q2, Q3, and Q4 conducting a drain current of 200 μA and each of Q6 and Q7 conducting a current of 400 μA. Design so that all transistors operate at 0.15-V overdrive voltages. Specify the W/L ratio required for each MOSFET. Present all results in a table. (b) Find the input common-mode range. (c) Find the allowable range of the output voltage. (d) With vA = vid/2 and vB = −vid/2, find the voltage gain vo /vid. Assume an Early voltage of 1.8 V.118a - 9.118 The two-stage op amp in Figure P9.114 is fabricated in a 65-nm technology having kn = 5.4 × kp = 540 μA/V2 and V tn = −Vtp = 0.35 V. The amplifier is operated with V DD = +1.2 V and VSS = 0 V.(a) With A and B at a dc voltage of VDD/2, perform a dc design that will result in each of Q1, Q2, Q3, and Q4 conducting a drain current of 200 μA and each of Q6 and Q7 conducting a current of 400 μA. Design so that all transistors operate at 0.15-V overdrive voltages. Specify the W/L ratio required for each MOSFET. Present all results in a table. (b) Find the input common-mode range. (c) Find the allowable range of the output voltage. (d) With vA = vid/2 and vB = −vid/2, find the voltage gain vo /vid. Assume an Early voltage of 1.8 V.

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images - 9.118 The two-stage op amp in Figure P9.114 is fabricated in a 65-nm technology having kn = 5.4 × kp = 540 μA/V2 and V tn = −Vtp = 0.35 V. The amplifier is operated with V DD = +1.2 V and VSS = 0 V.(a) With A and B at a dc voltage of VDD/2, perform a dc design that will result in each of Q1, Q2, Q3, and Q4 conducting a drain current of 200 μA and each of Q6 and Q7 conducting a current of 400 μA. Design so that all transistors operate at 0.15-V overdrive voltages. Specify the W/L ratio required for each MOSFET. Present all results in a table. (b) Find the input common-mode range. (c) Find the allowable range of the output voltage. (d) With vA = vid/2 and vB = −vid/2, find the voltage gain vo /vid. Assume an Early voltage of 1.8 V.

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