9.72 An NMOS amplifier, whose designed operating point is at V OV =0.3 V, is suspected to have a variability of Vt of ±5 mV, and of W/L and RD (independently) of ±1%. What is the worst-case input offset voltage you would expect to find? What is the major contribution to this total offset? If you used a variation of one of the drain resistors to reduce the output offset to zero and thereby compensate for the uncertainties (including that of the other RD), what percentage change from nominal would you require?

9.72 - 9.72 An NMOS amplifier, whose designed operating point is at V OV =0.3 V, is suspected to have a variability of Vt of ±5 mV, and of W/L and RD (independently) of ±1%. What is the worst-case input offset voltage you would expect to find? What is the major contribution to this total offset? If you used a variation of one of the drain resistors to reduce the output offset to zero and thereby compensate for the uncertainties (including that of the other RD), what percentage change from nominal would you require?

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images - 9.72 An NMOS amplifier, whose designed operating point is at V OV =0.3 V, is suspected to have a variability of Vt of ±5 mV, and of W/L and RD (independently) of ±1%. What is the worst-case input offset voltage you would expect to find? What is the major contribution to this total offset? If you used a variation of one of the drain resistors to reduce the output offset to zero and thereby compensate for the uncertainties (including that of the other RD), what percentage change from nominal would you require?

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