9.78 Two possible differential amplifier designs are considered, one using BJTs and the other MOSFETs. In both cases, the collector (drain) resistors are maintained within ±2% of nominal value. The MOSFETs are operated at VOV = 200 mV. What input offset voltage results in each case? What does the MOS V OS become if the devices are increased in width by a factor of 4 while the bias current is kept constant?

9.78 - 9.78 Two possible differential amplifier designs are considered, one using BJTs and the other MOSFETs. In both cases, the collector (drain) resistors are maintained within ±2% of nominal value. The MOSFETs are operated at VOV = 200 mV. What input offset voltage results in each case? What does the MOS V OS become if the devices are increased in width by a factor of 4 while the bias current is kept constant?

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images - 9.78 Two possible differential amplifier designs are considered, one using BJTs and the other MOSFETs. In both cases, the collector (drain) resistors are maintained within ±2% of nominal value. The MOSFETs are operated at VOV = 200 mV. What input offset voltage results in each case? What does the MOS V OS become if the devices are increased in width by a factor of 4 while the bias current is kept constant?

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