Category: Chapter 5 Sedra and smith MOS Field-Effect Transistors (MOSFETs)

Category: Chapter 5 Sedra and smith MOS Field-Effect Transistors (MOSFETs)

67

*5.67 Neglecting the channel-length-modulation effect, show that for the depletion-type NMOS transistor of Fig. P5.67, the i−v relationship is given by i = 1 2 k n(W/L)v2 −2Vtv for v ≥ Vt i = − 1 2 k n(W/L)Vt2 for v ≤ Vt (Recall that Vt is negative.) Sketch the i−v relationship for the case: V t = −2 V and kn(W/L) = 2 mA/V2.

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66

5.66 For a particular depletion-mode NMOS device, Vt = −2 V, knW/L = 200 μA/V2, and λ = 0.02 V−1. When operated at v GS = 0, what is the drain current that flows for v DS = 1 V, 2 V, 3 V, and 10 V? What does each of these currents become if the device width is doubled with L the same? With L also doubled?

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65

5.65 A depletion-type n-channel MOSFET with knW/L = 2 mA/V2 and V t = −3 V has its source and gate grounded. Find the region of operation and the drain current for v D = 0.1 V, 1 V, 3 V, and 5 V. Neglect the channel-length-modulation effect.

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64

*5.64 (a) Using the expression for iD in saturation and neglecting the channel-length modulation effect (i.e., let λ = 0), derive an expression for the per unit change in iD per °C ∂iD/iD/∂T in terms of the per unit change in kn per °C ∂kn/kn /∂T, the temperature coefficient of Vt in V/°C ∂Vt/∂T, and VGS and Vt. (b) If Vt decreases by 2 mV for every °C rise in temperature, find the temperature coefficient of kn that results in iD decreasing by 0.2%/°C when the NMOS transistor with Vt = 1 V is operated at VGS = 5 V

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63

5.63 A p-channel transistor operates in saturation with its source voltage 3 V lower than its substrate. For γ = 0.5 V1/2, 2φf = 0.75 V, and Vt0 = −0.7 V, find Vt.

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62

5.62 In a particular application, an n-channel MOSFET operates with VSB in the range 0 V to 4 V. If Vt0 is nominally 1.0 V, find the range of Vt that results if γ = 0.5 V1/2 and 2φf = 0.6 V. If the gate oxide thickness is increased by a factor of 4, what does the threshold voltage become?

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61

5.61 In the circuit of Fig. P5.61, transistors Q1 and Q2 have Vt = 0.7 V, and the process transconductance parameter kn = 125 μA/V2. Find V1, V2, and V3 for each of the following cases: (a) (W/L)1 = (W/L)2 = 20 (b) (W/L)1 = 1.5(W/L)2 = 20

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60

*5.60 For the devices in the circuit of Fig. P5.60,  Vt  = 1 V, λ = 0, μnCox = 50 μA/V2, L = 1 μm, and W = 10 μm. Find V2 and I2. How do these values change if Q3 and Q4 are made to have W = 100 μm?

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59

5.59 For the circuits in Fig. P5.59, μnCox = 3 μpCox = 270 μA/V2,  Vt  = 0.5 V, λ = 0, L = 1 μm, and W = 3 μm, unless otherwise specified. Find the labeled currents and voltages.

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58

*5.58 For the circuit in Fig. P5.58: (a) Show that for the PMOS transistor to operate in saturation, the following condition must be satisfied: IR ≤| Vtp | (b) If the transistor is specified to have |Vtp| = 1 V and kp = 0.2 mA/V2, and for I = 0.1 mA, find the voltages V SD and VSG for R = 0, 10 k, 30 k, and 100 k.

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