# Category: CHAPTER 9 Differential and Multistage Amplifiers #### 2.4 Given the circuit in Fig. P2.4, find the voltage across each resistor and the power dissipated in each

... #### 2.3 Determine the voltage across the resistor in Fig. P2.3 and the power dissipated

... #### 2.2 Determine the current and power dissipated in the resistors in Fig. P2.2

... #### 2.1 Determine the current and power dissipated in the resistor in Fig. P2.1

... #### 6.2 Two transistors, fabricated with the same technology but having different junction areas, when operated at a base-emitter voltage of 0.75 V, have collector currents of 0.5 mA and 2 mA. Find I S for each device. What are the relative junction areas?

... #### 6.1 The terminal voltages of various npn transistors are measured during operation in their respective circuits with the following results: In this table, where the entries are in volts, 0 indicates the reference terminal to which the black (negative) probe of the voltmeter is connected. For each case, identify the mode of operation of the transistor.

... #### D ***9.128 In the CMOS op amp shown in Fig. P9.128, all MOS devices have  Vt  = 1V, μn Cox =2 μpCox =40 μA/V2,  VA  = 50 V, and L = 5 μm. Device widths are indicated on the diagram as multiples of W, where W = 5 μm. (a) Design R to provide a 10-μA reference current. (b) Assuming vO =0 V, as established by external feedback, perform a bias analysis, finding all the labeled node voltages, and VGS and ID for all transistors. (c) Provide in table form ID, VGS, gm, and ro for all devices. (d) Calculate the voltage gain vo/v+ −v−, the input resistance, and the output resistance. (e) What is the input common-mode range? (f) What is the output signal range for no load?(g) For what load resistance connected to ground is the output negative voltage limited to −1 V before Q7 begins to conduct? (h) For a load resistance one-tenth of that found in (g), what is the output signal swing?

... #### D ***9.127 For the circuit shown in Fig. P9.127, which uses a folded cascode involving transistor Q3, all transistors have  V BE  = 0.7 V for the currents involved, VA =200 V, and β = 100. The circuit is relatively conventional except for Q5, which operates in a Class B mode (we will study this in Chapter 12) to provide an increased negative output swing for low-resistance loads.(a) Perform a bias calculation assuming  VBE  = 0.7 V, high β, VA =∞, v+ =v− =0 V, and vO is stabilized by feedback to about 0 V. Find R so that the reference current I REF is 100 μA. What are the voltages at all the labeled nodes? (b) Provide in tabular form the bias currents in all transistors together with gm and ro for the signal transistors (Q1, Q2, Q3, Q4, and Q5) and ro for QC, QD, and QG. (c) Now, using β =100, find the voltage gain vo/(v+ −v−), and in the process, verify the polarity of the input terminals.(d) Find the input and output resistances. (e) Find the input common-mode range for linear operation. (f) For no load, what is the range of available output voltages, assuming  VCEsat  = 0.3 V? (g) Now consider the situation with a load resistance connected from the output to ground. At the positive and negative limits of the output signal swing, find the smallest load resistance that can be driven if one or the other of Q1 or Q2 is allowed to cut off.

... #### **9.126 The MOS differential amplifier shown in Fig. P9.126 utilizes three current mirrors for signal transmission: Q4−Q6 has a transmission factor of 2 [i.e., (W/L)6/(W/L)4 = 2], Q3−Q5 has a transmission factor of 1, and Q7−Q8 has a transmission factor of 2. All transistors are sized to operate at the same overdrive voltage,  VOV . All transistors have the same Early voltage  VA . Q3 Q4 Q1 Q2 VDD VDD Q6 Q7 Q5 Q8 vo I Figure P9.126 (a) Provide in tabular form the values of ID, gm, and ro of each of the eight transistors in terms of I, VOV, and VA. (b) Show that the differential voltage gain Ad is given by A d = 2gm1ro6 ro8 = VA/VOV (c) Show that the CM gain is given by  A cm   ro 6 ro8 R SS 1 gm7ro7 where R SS is the output resistance of the bias current source I. [Hint: Replace each of Q1 and Q2 together with their source resistance 2R SS with a controlled current-source v icm/2RSS and an output resistance. For each current mirror, the current transfer ratio is given by A i  Ai (ideal) 1− gm1ro  where gm and ro are the parameters of the input transistor of the mirror. (see Problem 9.125 above.)] (d) If the current source I is implemented using a simple mirror and the MOS transistor is operated at the same V OV, show that the CMRR is given by CMRR = 4VA/VOV2 (e) Find the input CM range and the output linear range in terms of V DD,  Vt  , and  VOV

... #### 9.125 For the current mirror in Fig. P9.125, replace the transistors with their hybrid-π models and show that: R i = 1 gm1 ro 1 A is  Ais  ideal1− gm11ro1  A is  ideal = gm2/gm1 R o = ro2 where A is denotes the short-circuit current gain

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