D 9.6 Design the circuit in Fig. P9.6 to obtain a dc voltage of +0.1 V at each of the drains of Q1 and Q2 when v G1 = vG2 = 0 V. Operate all transistors at VOV = 0.15 V Q1 Q2 vG1 vG2 Q3 VDD 0.9 V VSS 0.9 V 0.9 V R D RD Q4 R 0.1 mA 0.4 mA Figure P9.6and assume that for the process technology in which the circuit is fabricated, Vtn = 0.4 V and μnCox = 400 μA/V2. Neglect channel-length modulation. Determine the values of R, RD, and the W/L ratios of Q1, Q2, Q3, and Q4. What is the input common-mode voltage range for your design?

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images - D 9.6 Design the circuit in Fig. P9.6 to obtain a dc voltage of +0.1 V at each of the drains of Q1 and Q2 when v G1 = vG2 = 0 V. Operate all transistors at VOV = 0.15 V Q1 Q2 vG1 vG2 Q3 VDD 0.9 V VSS 0.9 V 0.9 V R D RD Q4 R 0.1 mA 0.4 mA Figure P9.6and assume that for the process technology in which the circuit is fabricated, Vtn = 0.4 V and μnCox = 400 μA/V2. Neglect channel-length modulation. Determine the values of R, RD, and the W/L ratios of Q1, Q2, Q3, and Q4. What is the input common-mode voltage range for your design?

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